1. Field of the Invention
The present invention relates to an image sensor. More particularly, the present invention relates to a CMOS image sensor and fabricating method the same.
2. Discussion of the Related Art
Generally, an image sensor is a device which is capable of converting an optical image into an electric signal. Within the image sensors industry, the sensors are typically categorized as either CMOS (complementary metal-oxide-silicon) image sensors or CCS (charge coupled device) image sensors.
The CCD image sensors have superior noise and photo sensitivity characteristics when compared to the CMOS image sensors, but have difficulties achieving the density required for highly integrated systems and reducing their high power consumption. On the contrary, the CMOS image sensors use simpler processes and have relatively lower power consumption characteristics, making them more suitable for the density requirements of highly integrated systems than the CCD image sensors.
As the technology for fabricating semiconductor devices continues to develop, many efforts have been focused on researching and developing the CMOS image sensor. Because of these advances, improved fabricating technologies and improved characteristics of the CMOS image sensors have been discovered.
In one CMOS image sensor fabricating method currently used in the art, both salicidation and silicidation processes are simultaneously performed, making it difficult to adequately form a borderless contact in a non-salicide area. Thus, the salicide blocking oxide layer is formed in the non-salicide area with an increased thickness, creating a height difference between the pixel area and logic area. This difference in height creates problems when using a PMD (pre-metal dielectric) liner nitride layer as a contact etch stop layer.
More specifically, when an etching process is performed in order to form the contact, the etch stop time used to create the contact etch stop layer in the non-salicide area is different than the etch stop time used to form the contact etch stop layer in a salicide area.
When the contact etch stop layer in the salicide area is used as a contact etch stop target, the oxide layer beneath the contact etch stop layer in the non-salicide area is also etched. Thus, when the contact etch stop layer in the salicide area is etched, an oxide layer in an STI area of the non-salicide area is etched as well. Because a portion of the oxide layer in the STI area is etched, the leakage current in the borderless contact area is increased.
In particular, referring to FIG. 1, in the method for fabricating a CMOS image sensor of the related art, a pixel area having a photodiode 1 is formed on an epitaxial layer using an epitaxy process. A logic area having a plurality of devices for signal processing is formed on a semiconductor substrate, STI CMP is carried out to form a STI (shallow trench isolation) layer 2, and a gate oxide layer pattern 3 and a gate polysilicon pattern 4 are then formed to provide a gate area.
After forming a sidewall, source and drain 5 are formed by ion implantation process. A plurality of silicide layers 6 are then formed in the logic area only.
After a plurality of the silicide layers 6 have been formed, a PMD liner nitride layer 7 and a PSG (phosphosilicate glass) layer 9 are formed. CMP is carried out on the PSG layer 9 to planarize the surface of the PSG layer 9. A contact area 8 is then formed by a contact forming process. If the method is carried out in the above-explained manner, a portion of the oxide in the oxide layer is lost in a non-salicide area, i.e., in the area extending the STI area 2 beneath the contact 8 in the pixel area. If the oxide is lost in the STI area 2, however, the source and drain junction depth under the contact 8 is reduced, resulting in an increased electric field, and increased current leakage.